1. Field of the Invention
The present invention relates to a memory circuit and a method of generating the memory circuit, and in particular to a memory circuit for use in a semiconductor integrated circuit in combination with logic circuits and a method of generating such a memory circuit.
2. Description of the Background Art
With advances in microfabrication technology, the performance of semiconductor integrated circuits is improving day by day. In recent video apparatuses and information communication apparatuses, in order to achieve a reduction in cost and power consumption of the system, generally, a large-capacity memory circuit is mounted on a semiconductor integrated circuit, and computation, such as image processing, is performed within the semiconductor integrated circuit. In addition, with an increase in complexity of the system, the capacity of the memory mounted on the semiconductor integrated circuit has been significantly increased. For these reasons, in semiconductor integrated circuits having logic circuits and memory circuits mounted thereon, such as system LSIs, the proportion of the area occupied by memory circuits in relation to the entire chip has been increasing.
An example of semiconductor integrated circuits having logic circuits and memory circuits mounted thereon, such as those described above, is described in Japanese Laid-Open Patent Publication No. 63-91895. The publication describes a semiconductor integrated circuit including RAMs (memory circuits) which are not provided with input and output buffers; a gate array (logic circuits) having a plurality of input and output buffers for the RAMs.
In a semiconductor integrated circuit having logic circuits and memory circuits mounted thereon, such as a system LSI, as the memory capacity to be included on the semiconductor integrated circuit increases, the layout becomes inefficient and the chip area increases, and accordingly the problem of increase in chip cost arises. With reference to FIG. 9, the problem will be described below.
FIG. 9 is a diagram illustrating a configuration of a conventional semiconductor integrated circuit. A semiconductor integrated circuit 91 shown in FIG. 9 is a system LSI which includes external connection terminals 92 each for establishing a connection to an external circuit; a logic circuit section 93; and two memory circuits 94. Note that FIG. 9 shows only those signal lines that are necessary for the following description. Although not shown in the drawing, each memory circuit 94 includes a memory cell array having arranged therein memory cells in a matrix form; and a peripheral circuit section for writing and reading the memory cell array.
In the semiconductor integrated circuit 91 shown in FIG. 9, in the case of connecting between the external connection terminals 92 and terminals of the logic circuit section 93, if the area of the memory circuits 94 is small, the connection can be established by short straight wires. However, if the area of the memory circuits 94 is large, the wires connecting between the external connection terminals 92 and the terminals of the logic circuit section 93 need to be passed through a narrow region sandwiched between the two memory circuits 94 in a winding manner, resulting in an increase in wire length. If the wire length is increased, the parasitic capacitance and the resistance component are increased, whereby distortion occurs in a signal propagating through the wire and the propagation speed of the signal is degraded. In order to increase the propagation speed of a signal even where the wire length is long, there is a need to arrange in the middle of the wires buffer circuits 95 having an amplification effect. However, the buffer circuit 95 is a circuit element including a transistor, and thus cannot be arranged at a location where the memory cells are arranged. Therefore, the wire connecting between the external connection terminal 92 and the logic circuit section 93 is connected to the buffer circuit 95 so as to route around the memory circuit 94. As described above, in the semiconductor integrated circuit 91, as the area of the memory circuits 94 increases, the layout becomes inefficient and the chip area increases, resulting in an increase in chip cost.